Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. The programmable resources such as, e.g., programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells.
ICs, such as FPGAs, can include input/output (IO) circuitry capable of meeting the specifications of particular memory circuits. One type of dynamic random access memory (DRAM) used in today's high-bandwidth applications is double data rate 3 (DDR3) memory as defined by the Joint Electron Devices Engineering Council (JEDEC). IO circuitry that writes to DDR3 memory is required to meet two specific specifications: (1) the output signals must have low jitter; and (2) the data must be able to be delayed with respect to the clock by more than 1 ns to implement a “write leveling” technique. DDR3 memory includes memory components with a daisy-chained clock. Such topology of memory chips on a DDR3 memory module results in a skew delay between the clock and the data. A technique known as “write leveling” must be employed to compensate for this skew delay.
Programmable ICs, such as an FPGA, can include a global clock that is distributed throughout the programmable fabric. The global clock can be used to clock the IO circuitry driving DDR3 memory, as well as providing a clock for use by the DDR3 memory. Because of the multitude of outputs and fabric switching on an FPGA, the global clock lines can include a substantial amount of noise. Experimental data has shown that global clock jitter in a typical FPGA can exceed 100 ps. DDR3 memories presently can have a data rate of 1600 megabits per second (Mbps). The DDR3 specification requires that the period jitter cannot exceed 140 ps. If the global clock jitter is over 100 ps, a specification of 140 ps would be difficult if not impossible to meet.
Further, on a memory module of DDR3 chips (e.g., a dual inline memory module (DIMM)), the delay from the first memory chip to the last memory chip can exceed 1.2 ns. One technique to implement the necessary write leveling is to use a delay line to delay the data with respect to the clock. One problem with this approach, however, is that every tap used in the delay line will add a finite amount of deterministic jitter to the data. With a 1600 Mbps bandwidth, the data eye is 625 ps wide. A 1.2 ns delay of the data through a delay line to implement write leveling, for example, could add 70 to 80 ps of deterministic jitter to the data. In such an example, almost ⅓ of the output eye would be lost before including any losses due to the IO circuitry, the package, and the medium.
Accordingly, there exists a need in the art for a memory write interface in an IC that overcomes the aforementioned disadvantages.